

module frv_isq_sob (  // Store Order Buffer
    input                       clk             ,
    input                       rst_n           ,
    input                       pd_rst          ,
    // Store Request
    input                       sob_wreq        ,
    input [5:0]     sob_inst_id     ,   
    // ISQ Flush
    input                       sob_flush       ,
    input [5:0]     sob_flush_id    ,
    // Store Buffer Selection
    output[5:0]     sob_head_inst_id,
    output                      sob_head_vld    ,

    input                       sob_rreq        ,

    output                      sob_rdy          
);

wire [4:0] sob_wprt,sob_wprt_nxt;
wire [4:0] sob_rprt,sob_rprt_nxt;

wire [5:0]          entry_inst_id_0,entry_inst_id_nxt_0;
wire                            entry_vld_0,entry_vld_nxt_0        ;
wire                            entry_wen_0        ;
wire [5:0]          entry_inst_id_1,entry_inst_id_nxt_1;
wire                            entry_vld_1,entry_vld_nxt_1        ;
wire                            entry_wen_1        ;
wire [5:0]          entry_inst_id_2,entry_inst_id_nxt_2;
wire                            entry_vld_2,entry_vld_nxt_2        ;
wire                            entry_wen_2        ;
wire [5:0]          entry_inst_id_3,entry_inst_id_nxt_3;
wire                            entry_vld_3,entry_vld_nxt_3        ;
wire                            entry_wen_3        ;
wire [5:0]          entry_inst_id_4,entry_inst_id_nxt_4;
wire                            entry_vld_4,entry_vld_nxt_4        ;
wire                            entry_wen_4        ;
wire [5:0]          entry_inst_id_5,entry_inst_id_nxt_5;
wire                            entry_vld_5,entry_vld_nxt_5        ;
wire                            entry_wen_5        ;
wire [5:0]          entry_inst_id_6,entry_inst_id_nxt_6;
wire                            entry_vld_6,entry_vld_nxt_6        ;
wire                            entry_wen_6        ;
wire [5:0]          entry_inst_id_7,entry_inst_id_nxt_7;
wire                            entry_vld_7,entry_vld_nxt_7        ;
wire                            entry_wen_7        ;
wire [5:0]          entry_inst_id_8,entry_inst_id_nxt_8;
wire                            entry_vld_8,entry_vld_nxt_8        ;
wire                            entry_wen_8        ;
wire [5:0]          entry_inst_id_9,entry_inst_id_nxt_9;
wire                            entry_vld_9,entry_vld_nxt_9        ;
wire                            entry_wen_9        ;
wire [5:0]          entry_inst_id_10,entry_inst_id_nxt_10;
wire                            entry_vld_10,entry_vld_nxt_10        ;
wire                            entry_wen_10        ;
wire [5:0]          entry_inst_id_11,entry_inst_id_nxt_11;
wire                            entry_vld_11,entry_vld_nxt_11        ;
wire                            entry_wen_11        ;
wire [5:0]          entry_inst_id_12,entry_inst_id_nxt_12;
wire                            entry_vld_12,entry_vld_nxt_12        ;
wire                            entry_wen_12        ;
wire [5:0]          entry_inst_id_13,entry_inst_id_nxt_13;
wire                            entry_vld_13,entry_vld_nxt_13        ;
wire                            entry_wen_13        ;
wire [5:0]          entry_inst_id_14,entry_inst_id_nxt_14;
wire                            entry_vld_14,entry_vld_nxt_14        ;
wire                            entry_wen_14        ;
wire [5:0]          entry_inst_id_15,entry_inst_id_nxt_15;
wire                            entry_vld_15,entry_vld_nxt_15        ;
wire                            entry_wen_15        ;

wire                            flush_vec_0        ;
wire                            age_cmp_res_0        ;
wire                            flush_vec_1        ;
wire                            age_cmp_res_1        ;
wire                            flush_vec_2        ;
wire                            age_cmp_res_2        ;
wire                            flush_vec_3        ;
wire                            age_cmp_res_3        ;
wire                            flush_vec_4        ;
wire                            age_cmp_res_4        ;
wire                            flush_vec_5        ;
wire                            age_cmp_res_5        ;
wire                            flush_vec_6        ;
wire                            age_cmp_res_6        ;
wire                            flush_vec_7        ;
wire                            age_cmp_res_7        ;
wire                            flush_vec_8        ;
wire                            age_cmp_res_8        ;
wire                            flush_vec_9        ;
wire                            age_cmp_res_9        ;
wire                            flush_vec_10        ;
wire                            age_cmp_res_10        ;
wire                            flush_vec_11        ;
wire                            age_cmp_res_11        ;
wire                            flush_vec_12        ;
wire                            age_cmp_res_12        ;
wire                            flush_vec_13        ;
wire                            age_cmp_res_13        ;
wire                            flush_vec_14        ;
wire                            age_cmp_res_14        ;
wire                            flush_vec_15        ;
wire                            age_cmp_res_15        ;

wire [4:0] flush_num;

isq_entry_num_compute _sob_flush_num_compute(
.entry_vld_0        (flush_vec_0),
.entry_vld_1        (flush_vec_1),
.entry_vld_2        (flush_vec_2),
.entry_vld_3        (flush_vec_3),
.entry_vld_4        (flush_vec_4),
.entry_vld_5        (flush_vec_5),
.entry_vld_6        (flush_vec_6),
.entry_vld_7        (flush_vec_7),
.entry_vld_8        (flush_vec_8),
.entry_vld_9        (flush_vec_9),
.entry_vld_10        (flush_vec_10),
.entry_vld_11        (flush_vec_11),
.entry_vld_12        (flush_vec_12),
.entry_vld_13        (flush_vec_13),
.entry_vld_14        (flush_vec_14),
.entry_vld_15        (flush_vec_15),
.entry_num        (flush_num)
);

assign sob_wprt_nxt = sob_flush ? sob_wprt - flush_num :
                      sob_wreq  ? sob_wprt + 1 :
                      sob_wprt;
assign sob_rprt_nxt = sob_rreq  ? sob_rprt + 1 : 
                      sob_rprt;

// assign sob_wprt_nxt = sob_wreq  ? sob_wprt + 1 :
//                       sob_wprt;
// assign sob_rprt_nxt = sob_rreq  ? sob_rprt + 1 : 
//                       sob_rprt;

assign sob_rdy = ~({~sob_wprt[4],sob_wprt[4-1:0]} == sob_rprt);

assign sob_head_inst_id = ({(5+1){sob_rprt[4-1:0] == 0}} & entry_inst_id_0) 
            | ({(5+1){sob_rprt[4-1:0] == 1}} & entry_inst_id_1) 
            | ({(5+1){sob_rprt[4-1:0] == 2}} & entry_inst_id_2) 
            | ({(5+1){sob_rprt[4-1:0] == 3}} & entry_inst_id_3) 
            | ({(5+1){sob_rprt[4-1:0] == 4}} & entry_inst_id_4) 
            | ({(5+1){sob_rprt[4-1:0] == 5}} & entry_inst_id_5) 
            | ({(5+1){sob_rprt[4-1:0] == 6}} & entry_inst_id_6) 
            | ({(5+1){sob_rprt[4-1:0] == 7}} & entry_inst_id_7) 
            | ({(5+1){sob_rprt[4-1:0] == 8}} & entry_inst_id_8) 
            | ({(5+1){sob_rprt[4-1:0] == 9}} & entry_inst_id_9) 
            | ({(5+1){sob_rprt[4-1:0] == 10}} & entry_inst_id_10) 
            | ({(5+1){sob_rprt[4-1:0] == 11}} & entry_inst_id_11) 
            | ({(5+1){sob_rprt[4-1:0] == 12}} & entry_inst_id_12) 
            | ({(5+1){sob_rprt[4-1:0] == 13}} & entry_inst_id_13) 
            | ({(5+1){sob_rprt[4-1:0] == 14}} & entry_inst_id_14) 
            | ({(5+1){sob_rprt[4-1:0] == 15}} & entry_inst_id_15) 
                 ;

assign sob_head_vld = ((sob_rprt[4-1:0] == 0) & entry_vld_0) 
            | ((sob_rprt[4-1:0] == 1) & entry_vld_1) 
            | ((sob_rprt[4-1:0] == 2) & entry_vld_2) 
            | ((sob_rprt[4-1:0] == 3) & entry_vld_3) 
            | ((sob_rprt[4-1:0] == 4) & entry_vld_4) 
            | ((sob_rprt[4-1:0] == 5) & entry_vld_5) 
            | ((sob_rprt[4-1:0] == 6) & entry_vld_6) 
            | ((sob_rprt[4-1:0] == 7) & entry_vld_7) 
            | ((sob_rprt[4-1:0] == 8) & entry_vld_8) 
            | ((sob_rprt[4-1:0] == 9) & entry_vld_9) 
            | ((sob_rprt[4-1:0] == 10) & entry_vld_10) 
            | ((sob_rprt[4-1:0] == 11) & entry_vld_11) 
            | ((sob_rprt[4-1:0] == 12) & entry_vld_12) 
            | ((sob_rprt[4-1:0] == 13) & entry_vld_13) 
            | ((sob_rprt[4-1:0] == 14) & entry_vld_14) 
            | ((sob_rprt[4-1:0] == 15) & entry_vld_15) 
                 ;

//Flush Control 
rob_id_cmpy #(5+1) rob_id_cmpy_0(entry_inst_id_0,sob_flush_id,age_cmp_res_0);
assign flush_vec_0 = entry_vld_0 && sob_flush && age_cmp_res_0;
rob_id_cmpy #(5+1) rob_id_cmpy_1(entry_inst_id_1,sob_flush_id,age_cmp_res_1);
assign flush_vec_1 = entry_vld_1 && sob_flush && age_cmp_res_1;
rob_id_cmpy #(5+1) rob_id_cmpy_2(entry_inst_id_2,sob_flush_id,age_cmp_res_2);
assign flush_vec_2 = entry_vld_2 && sob_flush && age_cmp_res_2;
rob_id_cmpy #(5+1) rob_id_cmpy_3(entry_inst_id_3,sob_flush_id,age_cmp_res_3);
assign flush_vec_3 = entry_vld_3 && sob_flush && age_cmp_res_3;
rob_id_cmpy #(5+1) rob_id_cmpy_4(entry_inst_id_4,sob_flush_id,age_cmp_res_4);
assign flush_vec_4 = entry_vld_4 && sob_flush && age_cmp_res_4;
rob_id_cmpy #(5+1) rob_id_cmpy_5(entry_inst_id_5,sob_flush_id,age_cmp_res_5);
assign flush_vec_5 = entry_vld_5 && sob_flush && age_cmp_res_5;
rob_id_cmpy #(5+1) rob_id_cmpy_6(entry_inst_id_6,sob_flush_id,age_cmp_res_6);
assign flush_vec_6 = entry_vld_6 && sob_flush && age_cmp_res_6;
rob_id_cmpy #(5+1) rob_id_cmpy_7(entry_inst_id_7,sob_flush_id,age_cmp_res_7);
assign flush_vec_7 = entry_vld_7 && sob_flush && age_cmp_res_7;
rob_id_cmpy #(5+1) rob_id_cmpy_8(entry_inst_id_8,sob_flush_id,age_cmp_res_8);
assign flush_vec_8 = entry_vld_8 && sob_flush && age_cmp_res_8;
rob_id_cmpy #(5+1) rob_id_cmpy_9(entry_inst_id_9,sob_flush_id,age_cmp_res_9);
assign flush_vec_9 = entry_vld_9 && sob_flush && age_cmp_res_9;
rob_id_cmpy #(5+1) rob_id_cmpy_10(entry_inst_id_10,sob_flush_id,age_cmp_res_10);
assign flush_vec_10 = entry_vld_10 && sob_flush && age_cmp_res_10;
rob_id_cmpy #(5+1) rob_id_cmpy_11(entry_inst_id_11,sob_flush_id,age_cmp_res_11);
assign flush_vec_11 = entry_vld_11 && sob_flush && age_cmp_res_11;
rob_id_cmpy #(5+1) rob_id_cmpy_12(entry_inst_id_12,sob_flush_id,age_cmp_res_12);
assign flush_vec_12 = entry_vld_12 && sob_flush && age_cmp_res_12;
rob_id_cmpy #(5+1) rob_id_cmpy_13(entry_inst_id_13,sob_flush_id,age_cmp_res_13);
assign flush_vec_13 = entry_vld_13 && sob_flush && age_cmp_res_13;
rob_id_cmpy #(5+1) rob_id_cmpy_14(entry_inst_id_14,sob_flush_id,age_cmp_res_14);
assign flush_vec_14 = entry_vld_14 && sob_flush && age_cmp_res_14;
rob_id_cmpy #(5+1) rob_id_cmpy_15(entry_inst_id_15,sob_flush_id,age_cmp_res_15);
assign flush_vec_15 = entry_vld_15 && sob_flush && age_cmp_res_15;

//Store Reuqest
assign entry_wen_0          = (sob_wprt[4-1:0] == 0 && sob_wreq) || (sob_rprt[4-1:0] == 0 && sob_rreq) || flush_vec_0;
assign entry_inst_id_nxt_0  = sob_inst_id ;
assign entry_vld_nxt_0      = (sob_wprt[4-1:0] == 0 && sob_wreq) && ~(sob_rprt[4-1:0] == 0 && sob_rreq) && ~flush_vec_0;
assign entry_wen_1          = (sob_wprt[4-1:0] == 1 && sob_wreq) || (sob_rprt[4-1:0] == 1 && sob_rreq) || flush_vec_1;
assign entry_inst_id_nxt_1  = sob_inst_id ;
assign entry_vld_nxt_1      = (sob_wprt[4-1:0] == 1 && sob_wreq) && ~(sob_rprt[4-1:0] == 1 && sob_rreq) && ~flush_vec_1;
assign entry_wen_2          = (sob_wprt[4-1:0] == 2 && sob_wreq) || (sob_rprt[4-1:0] == 2 && sob_rreq) || flush_vec_2;
assign entry_inst_id_nxt_2  = sob_inst_id ;
assign entry_vld_nxt_2      = (sob_wprt[4-1:0] == 2 && sob_wreq) && ~(sob_rprt[4-1:0] == 2 && sob_rreq) && ~flush_vec_2;
assign entry_wen_3          = (sob_wprt[4-1:0] == 3 && sob_wreq) || (sob_rprt[4-1:0] == 3 && sob_rreq) || flush_vec_3;
assign entry_inst_id_nxt_3  = sob_inst_id ;
assign entry_vld_nxt_3      = (sob_wprt[4-1:0] == 3 && sob_wreq) && ~(sob_rprt[4-1:0] == 3 && sob_rreq) && ~flush_vec_3;
assign entry_wen_4          = (sob_wprt[4-1:0] == 4 && sob_wreq) || (sob_rprt[4-1:0] == 4 && sob_rreq) || flush_vec_4;
assign entry_inst_id_nxt_4  = sob_inst_id ;
assign entry_vld_nxt_4      = (sob_wprt[4-1:0] == 4 && sob_wreq) && ~(sob_rprt[4-1:0] == 4 && sob_rreq) && ~flush_vec_4;
assign entry_wen_5          = (sob_wprt[4-1:0] == 5 && sob_wreq) || (sob_rprt[4-1:0] == 5 && sob_rreq) || flush_vec_5;
assign entry_inst_id_nxt_5  = sob_inst_id ;
assign entry_vld_nxt_5      = (sob_wprt[4-1:0] == 5 && sob_wreq) && ~(sob_rprt[4-1:0] == 5 && sob_rreq) && ~flush_vec_5;
assign entry_wen_6          = (sob_wprt[4-1:0] == 6 && sob_wreq) || (sob_rprt[4-1:0] == 6 && sob_rreq) || flush_vec_6;
assign entry_inst_id_nxt_6  = sob_inst_id ;
assign entry_vld_nxt_6      = (sob_wprt[4-1:0] == 6 && sob_wreq) && ~(sob_rprt[4-1:0] == 6 && sob_rreq) && ~flush_vec_6;
assign entry_wen_7          = (sob_wprt[4-1:0] == 7 && sob_wreq) || (sob_rprt[4-1:0] == 7 && sob_rreq) || flush_vec_7;
assign entry_inst_id_nxt_7  = sob_inst_id ;
assign entry_vld_nxt_7      = (sob_wprt[4-1:0] == 7 && sob_wreq) && ~(sob_rprt[4-1:0] == 7 && sob_rreq) && ~flush_vec_7;
assign entry_wen_8          = (sob_wprt[4-1:0] == 8 && sob_wreq) || (sob_rprt[4-1:0] == 8 && sob_rreq) || flush_vec_8;
assign entry_inst_id_nxt_8  = sob_inst_id ;
assign entry_vld_nxt_8      = (sob_wprt[4-1:0] == 8 && sob_wreq) && ~(sob_rprt[4-1:0] == 8 && sob_rreq) && ~flush_vec_8;
assign entry_wen_9          = (sob_wprt[4-1:0] == 9 && sob_wreq) || (sob_rprt[4-1:0] == 9 && sob_rreq) || flush_vec_9;
assign entry_inst_id_nxt_9  = sob_inst_id ;
assign entry_vld_nxt_9      = (sob_wprt[4-1:0] == 9 && sob_wreq) && ~(sob_rprt[4-1:0] == 9 && sob_rreq) && ~flush_vec_9;
assign entry_wen_10          = (sob_wprt[4-1:0] == 10 && sob_wreq) || (sob_rprt[4-1:0] == 10 && sob_rreq) || flush_vec_10;
assign entry_inst_id_nxt_10  = sob_inst_id ;
assign entry_vld_nxt_10      = (sob_wprt[4-1:0] == 10 && sob_wreq) && ~(sob_rprt[4-1:0] == 10 && sob_rreq) && ~flush_vec_10;
assign entry_wen_11          = (sob_wprt[4-1:0] == 11 && sob_wreq) || (sob_rprt[4-1:0] == 11 && sob_rreq) || flush_vec_11;
assign entry_inst_id_nxt_11  = sob_inst_id ;
assign entry_vld_nxt_11      = (sob_wprt[4-1:0] == 11 && sob_wreq) && ~(sob_rprt[4-1:0] == 11 && sob_rreq) && ~flush_vec_11;
assign entry_wen_12          = (sob_wprt[4-1:0] == 12 && sob_wreq) || (sob_rprt[4-1:0] == 12 && sob_rreq) || flush_vec_12;
assign entry_inst_id_nxt_12  = sob_inst_id ;
assign entry_vld_nxt_12      = (sob_wprt[4-1:0] == 12 && sob_wreq) && ~(sob_rprt[4-1:0] == 12 && sob_rreq) && ~flush_vec_12;
assign entry_wen_13          = (sob_wprt[4-1:0] == 13 && sob_wreq) || (sob_rprt[4-1:0] == 13 && sob_rreq) || flush_vec_13;
assign entry_inst_id_nxt_13  = sob_inst_id ;
assign entry_vld_nxt_13      = (sob_wprt[4-1:0] == 13 && sob_wreq) && ~(sob_rprt[4-1:0] == 13 && sob_rreq) && ~flush_vec_13;
assign entry_wen_14          = (sob_wprt[4-1:0] == 14 && sob_wreq) || (sob_rprt[4-1:0] == 14 && sob_rreq) || flush_vec_14;
assign entry_inst_id_nxt_14  = sob_inst_id ;
assign entry_vld_nxt_14      = (sob_wprt[4-1:0] == 14 && sob_wreq) && ~(sob_rprt[4-1:0] == 14 && sob_rreq) && ~flush_vec_14;
assign entry_wen_15          = (sob_wprt[4-1:0] == 15 && sob_wreq) || (sob_rprt[4-1:0] == 15 && sob_rreq) || flush_vec_15;
assign entry_inst_id_nxt_15  = sob_inst_id ;
assign entry_vld_nxt_15      = (sob_wprt[4-1:0] == 15 && sob_wreq) && ~(sob_rprt[4-1:0] == 15 && sob_rreq) && ~flush_vec_15;

//DFFs
dffr #(.DW(4+1)) sob_wprt_ff (clk,rst_n,1'b1,sob_wprt_nxt,sob_wprt);
dffr #(.DW(4+1)) sob_rprt_ff (clk,rst_n,1'b1,sob_rprt_nxt,sob_rprt);

dffr #(.DW(5+1)) entry_inst_id_ff_0 (clk,rst_n,entry_wen_0,entry_inst_id_nxt_0,entry_inst_id_0)  ;
dffr #(.DW(1))               entry_vld_ff_0     (clk,rst_n,entry_wen_0,entry_vld_nxt_0    ,entry_vld_0    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_1 (clk,rst_n,entry_wen_1,entry_inst_id_nxt_1,entry_inst_id_1)  ;
dffr #(.DW(1))               entry_vld_ff_1     (clk,rst_n,entry_wen_1,entry_vld_nxt_1    ,entry_vld_1    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_2 (clk,rst_n,entry_wen_2,entry_inst_id_nxt_2,entry_inst_id_2)  ;
dffr #(.DW(1))               entry_vld_ff_2     (clk,rst_n,entry_wen_2,entry_vld_nxt_2    ,entry_vld_2    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_3 (clk,rst_n,entry_wen_3,entry_inst_id_nxt_3,entry_inst_id_3)  ;
dffr #(.DW(1))               entry_vld_ff_3     (clk,rst_n,entry_wen_3,entry_vld_nxt_3    ,entry_vld_3    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_4 (clk,rst_n,entry_wen_4,entry_inst_id_nxt_4,entry_inst_id_4)  ;
dffr #(.DW(1))               entry_vld_ff_4     (clk,rst_n,entry_wen_4,entry_vld_nxt_4    ,entry_vld_4    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_5 (clk,rst_n,entry_wen_5,entry_inst_id_nxt_5,entry_inst_id_5)  ;
dffr #(.DW(1))               entry_vld_ff_5     (clk,rst_n,entry_wen_5,entry_vld_nxt_5    ,entry_vld_5    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_6 (clk,rst_n,entry_wen_6,entry_inst_id_nxt_6,entry_inst_id_6)  ;
dffr #(.DW(1))               entry_vld_ff_6     (clk,rst_n,entry_wen_6,entry_vld_nxt_6    ,entry_vld_6    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_7 (clk,rst_n,entry_wen_7,entry_inst_id_nxt_7,entry_inst_id_7)  ;
dffr #(.DW(1))               entry_vld_ff_7     (clk,rst_n,entry_wen_7,entry_vld_nxt_7    ,entry_vld_7    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_8 (clk,rst_n,entry_wen_8,entry_inst_id_nxt_8,entry_inst_id_8)  ;
dffr #(.DW(1))               entry_vld_ff_8     (clk,rst_n,entry_wen_8,entry_vld_nxt_8    ,entry_vld_8    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_9 (clk,rst_n,entry_wen_9,entry_inst_id_nxt_9,entry_inst_id_9)  ;
dffr #(.DW(1))               entry_vld_ff_9     (clk,rst_n,entry_wen_9,entry_vld_nxt_9    ,entry_vld_9    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_10 (clk,rst_n,entry_wen_10,entry_inst_id_nxt_10,entry_inst_id_10)  ;
dffr #(.DW(1))               entry_vld_ff_10     (clk,rst_n,entry_wen_10,entry_vld_nxt_10    ,entry_vld_10    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_11 (clk,rst_n,entry_wen_11,entry_inst_id_nxt_11,entry_inst_id_11)  ;
dffr #(.DW(1))               entry_vld_ff_11     (clk,rst_n,entry_wen_11,entry_vld_nxt_11    ,entry_vld_11    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_12 (clk,rst_n,entry_wen_12,entry_inst_id_nxt_12,entry_inst_id_12)  ;
dffr #(.DW(1))               entry_vld_ff_12     (clk,rst_n,entry_wen_12,entry_vld_nxt_12    ,entry_vld_12    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_13 (clk,rst_n,entry_wen_13,entry_inst_id_nxt_13,entry_inst_id_13)  ;
dffr #(.DW(1))               entry_vld_ff_13     (clk,rst_n,entry_wen_13,entry_vld_nxt_13    ,entry_vld_13    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_14 (clk,rst_n,entry_wen_14,entry_inst_id_nxt_14,entry_inst_id_14)  ;
dffr #(.DW(1))               entry_vld_ff_14     (clk,rst_n,entry_wen_14,entry_vld_nxt_14    ,entry_vld_14    )  ;
dffr #(.DW(5+1)) entry_inst_id_ff_15 (clk,rst_n,entry_wen_15,entry_inst_id_nxt_15,entry_inst_id_15)  ;
dffr #(.DW(1))               entry_vld_ff_15     (clk,rst_n,entry_wen_15,entry_vld_nxt_15    ,entry_vld_15    )  ;

endmodule

